About the Role
Title: Senior ASIC Verification Engineer
Location: Remote United States
Job Description:
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability – solving the world’s most demanding computational challenges with our next-generation networking solutions.
We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.
Cornelis Networks is hiring Mid-Level and Senior ASIC Verification Engineers with advanced skills and knowledge in key areas required to verify world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC design, emulation and post-silicon teams towards creating a first-pass silicon success. A preferrable candidate will have 10 + years of relevant experience in networking hardware verification, proven expertise in verifying one or more of the following: 50G, 100G, 400G Ethernet MAC/PCS protocols, UDP, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking.
Key Responsibilities:
- Participate in ground up development of UVM environments to verify RTL at block, unit, and SoC levels
- Develop and execute functional tests according to verification test plans
- Instrument TB for functional and code coverage and drive to closure based on the coverage metrics
- Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality
Preferred Qualifications:
- M. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
- 10 + years of relevant experience in networking hardware verification, proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking
- One or more scripting languages (TCL, Python, Perl, Shell-scripting)
- Track record of first-pass success in ASIC and Systems
Minimum Qualifications:
- 10 + years of experience with the following:
- Writing code using System Verilog Language
- Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools
- Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
- Experience in ground up testbench development
- Experience with revision control systems like Git or SVN etc.
- B. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering